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附录3:单片机控制板PCB图

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附录4:英文资料及中文翻译

1.英文资料

Asynchronous Serial Data Transmission

By far the most popular serial interface between a computer and its CRT terminal is the asynchronous serial interface. This interface is so called because the transmitted data and the received data are not synchronized over any extended period and therefore no special means of synchronizing the clocks at the transmitter and receiver is necessary. In fact, the asynchronous serial data link is a very old form of data transmission system and has its origin in the era of teleprinter.

Serial data transmission systems have been around for a long time and are found in the telephone ( human speech ), Morse code, semaphore, and even the smoke signals once used by native Americans. The fundamental problem encountered by all serial data transmission systems in how to split the incoming data stream into individual units (i.e., bits) and how to group these units into characters. For example, in Morse code the dots and dashes of a character are separated by an inter symbol space, while the individual characters are separated by an inter character space, which is three times the duration of an intersymbol space.

First we examine how the data stream is divided into individual bits and the bits grouped into characters in an asynchronous serial link. The key to the operation of link is both simple and ingenious. Fig. 2-1 gives the format of data transmitted over such a link. Mark Space

T Data bits parity stop Bit bit One character Example : Letter M=ASCII$4D=1001101 ( even parity ) Start 1 0 1 1 0 0 1 0 Stop

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Fig.2-1 Format of Asynchronous Serial Data

An asynchronous serial data link is said to be character oriented, as information is transmitted in the form of groups of bits called characters. These characters are invariable units comprising 7or 8 bits of “information” plus 2 to 4 control bits and frequently correspond to ASCII encoded characters. Initially, when no information is being transmitted, the line is an idle state. Traditionally, the idle state is referred to as the mark level. By convention this corresponds to a logical 1 level.

When the transmitter wishes to send data, it first places the line in a space level ( i.e., the complement of a mark ) for one element period. This element is called the start bit and has a duration of T seconds. The transmitter then sends the character, 1 bit at a time , by placing each successive bit on the line for a duration of T seconds, until all bits have been transmitted. Then a single parity bit is calculated by the transmitter and sent after the data bits. Finally, the transmitter sends a stop bit at a mark level ( I .e ., the same level as the idle state ) for one or two bit periods. Now the transmitter may send another character whenever it wishes.

At the receiving end of an asynchronous serial data link, the receiver continually monitors the line looking for a start bit. Once the start bit has been detected, the receiver waits until the end of the start bit and then samples the next N bits at their centers, using a clock generated locally by the receiver. As each incoming bit is sampled, it is used to construct a new character .When the received character has been assembled, its parity is calculated and compared with the received parity bit following the character. If they are not equal, a parity error flag is set to indicate a transmission error.

The most critical aspect of the system is the receiver timing. The falling edge of the start bit triggers the receiver’s local clock, which samples each incoming bit at its nominal center. Suppose the receiver clock waits T/2 seconds from the falling edge of the start bit and samples the incoming data every T seconds thereafter until the stop bit has been sampled. Fig .2-2 shows this situation. As the receiver’s clock is not synchronized with the transmitter clock, the sampling is not exact.

The most obvious disadvantage of asynchronous data transmission is the need for a start, parity, and stop bit for each transmitted character. If 7 bit characters are used, the overall efficiency is only 70%. A less obvious disadvantage is due to the character-oriented nature of the data link. Whenever the data link connects a CRT

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terminal to a computer, few problems arise, as the terminal is itself character oriented. However, if the dada link is being to, say, dump binary dada to a magnetic tape, problems arise. Start bit Mark T Space Seconds T/2 T/2 T/2

Beginneng Sampling End of

Of start bit center stop bit Synchronous Digital Hierarchy

T/2

SDH is an International Standard for high-speed synchronous optical telecommunication networks-a Synchronous Digital Hierarchy.

Work started on SDH standards in CCITT’s Study Group XVIII in June 1986. The objective was to produce a worldwide standard for synchronous transmission systems which provides network operators with a flexible and economic network. In November 1988 the first SDH standards were approved—G.707,G.708, and G.709. These standards define transmission rates, signal format, multiplexing structures and tributary mappings for the Network Node Interface ( NNI )—the international standard interface for Synchronous Digital Hierarchy.

In addition to defining standards covering the NII, CCITT also embarked on series of standards governing the operation of synchronous multiplexers ( G. 781, G.782 and G.783 ) and SDH Network Management ( G.784 ).It is the standardization of these aspects of SDH equipment that will deliver the flexibility required by network operators to cost-effectively manage the growth in bandwidth and provisioning of new customer services expected in the next decade .

The SDH standards are based on the principles of direct synchronous multiplexing which is the key to cost-effective and flexible telecommunication networking. In essence, it means that individual tributary signals may be multiplexed directly into a higher SDH signal without intermediate stages of multiplexing. SDH Network Elements can then be interconnected directly with obvious cost and equipment savings over the existing network.

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Advanced network management and maintenance capabilities are required to effectively manage the flexibility provided by SDH. Approximately 5% of the SDH signal structure is allocated to supporting advanced network management procedures and practices.

The SDH signal is capable of transporting all the common tributary signals found in today’s telecommunication networks. This means that SDH can be deployed as an overlay to the existing signal types. In addition, SDH has the flexibility to readily accommodate new types of customer service signals that network operators will wish to support in the future.

SDH can be used in all traditional telecommunications application areas. SDH therefore makes it possible for a unified telecommunication network infrastructure to evolve. The fact that SDH provides a single common standard for this telecommunications network means that equipment supplied by different manufacturers may be interconnected directly.

Now, let’s take a look at the network “building blocks” and how they are configured. These network elements are now all defined in CCITT standards and provide multiplexing or switching functions.

Line Terminal Multiplexer ( LTM ): LTM can accept a number of tributary signals and multiplex them to the appropriate optical SDH rate carrier, i . e . STM-1, STM-4 or STM-16 . The input tributaries can either be the existing PDH signals such as 2,34 and 140 Mbit/s or lower rate SDH signals. LTM forms the main gateway from the PDH to the SDH.

Add-drop Multiplexer ( ADM ) :a particular type of terminal multiplexer designed to operate in a through mode fashion . Within the ADM it is possible to add channels to, or drop channels from the “through” signal. ADM is generally available at the STM-1 and STM-4 interface rates and may add /drop a variety of tributary signals, I .e .2 ,34 or 140 Mbit/s .

The ADM function is one of the major advantages resulting from the SDH since the similar function within a PDH network , required banks of hardwired back-back terminals.

Synchronous DXC: these devices will from the cornerstone of the new synchronous digital hierarchy. They can function as semi-permanent switches for transmission channels and can switch at any level from64 kbit/s up to STM-1. Generally such devices have interface at STM-1 or STM-4 .The DXC can be rapidly reconfigured,

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